KiCad - PBC Editor #

Introduction #

In the last tutorial, we went from the basic design to a full schematic. Now, we will take the schematic and turn it into a PCB.

Setup #

From the main KiCad window, double click on the pcb file to open the pbc editor.

Configuring Page Settings #

Similar to the schematic, we first want to fill in relevent information. Click “Page Settings” and fill it in. Also select the desired paper size. Here I have selected 8.5x11 for easy printing in the US.

Click Ok when complete.

Configure the Board Settings #

Every PCB fab has different requirements that define their manufacturing capability. They will have posted on their website a list of their manufacturing specifications. For this example, we will use OshPark’s two layer prototyping specifications.

In PCB Editor, click on “Board Setup” in the top bar.

The “Board Setup” dialog has all of the definitions for the PCB layers, trace widths, etc. The most commonly adjusted settings are under “Net Classes”. These are the settings per net (i.e., Vdd, Vin, etc.). There is a “Default” net class that applies to all nets not explicitly defined. Now, we must compare the requirements from OshPark and ensure that our netclasses meet the requirements. For example, OshPark requires min trace spacing of 0.1524mm. The default netclass setting enforces 0.2mm trace spacing so that is sufficient for the design rules.

However, for sometimes we want different settings for different types of nets. In this example, let’s create a Power netclass for all of our power supply related nets. Click the “+” button and create a new netclass called “Power”. Keep all the same settings as “Default” except for the Track Width. Increase the Track Width to 0.5mm (you can use the “PCB Calculator” KiCad app to figure out the required trace widths). Any net with the Power class can handle more current. In the next section we will assign nets to each class.

Import Netlist #

In the main PCB Editor window click the “Update PCB from Schematic” button.

KiCad will now export the netlist from the schematic and import all the footprints and nets into the PCB editor. Keep the default boxes selected in the dialog the pops up and click “Update PCB”.

All of the footprints and a light blue “ratsnest” denoting all the required connections will populate in the editor. Now we can assign nets to the netclasses. Open the Board Settings again and under Net Classes, assign GND, Vdd and Vss to the Power Net Class.

Now any wires drawn for the GND, Vdd and Vss nets will have the proper dimensions.

PCB Design #

Floor Planning #

Now we can place the components together. Using the “m” move hot key and the “r” rotate hot key, place the components such that the ratsnests are the least tangled. There is no one “right” way to floor plan the PCB, but there are a few good guidelines.

• Pretty layouts are more likely to work.
• Make it easy to assemble.
• Keep decoupling capacitors as close to the devices the are regulating as possible.
• Keep high frequency signals away from other things
• Less vias is generally better.
• Ground plains are generally good.

After a little work, we can get a floor plan like the following.

Layers and Wiring #

A PCB is made of different layers (metals, dielectrics, solder masks, silk screens, etc.) that are all glued together. In the PCB editor, we are drawing on each of these layers. We can see all of the available layers in the right column. Most layers correspond to a physical layer. For example, F.Cu is the front coper layer. Others are for information or placeement alighment and don’t correspond to any physical layer (F.Fab, B.Fab, etc.). To help make things more clear, we have hidden the F.Fab layer). When we draw in the PCB editor, we draw on the selected layer.

So, to wire the footprints together, we must select one of the coper layers. Let’s start by selecting F.Cu and wiring the non-power signals. Hover over the Port 4 of J1 and press the “x” key to start wiring. Move the mouse over to the bottom port of R1 and click to complete the route.

Repeat the process to finish wiring in all signal nets.

Now, select the back coper layer (B.Fu) and wire in all Vdd and Vss, but not GND.

Ground Planes #

To wire GND, we will create ground plans in both the top and bottom coper. There are two steps, first, we will draw an “edge cut” to denote the boarders of the board and then we will draw fill for GND in the board. Select the Edge.Cuts layer and select the rectangle tool.

Draw a rectangle around the footprints to define the board edge. Since we want the pins to hang off the edge of the board, we will not draw the Edge.cuts entirely around the pins. Similarly for the tuning screw on the potentiometer.

Select the F.Cu layer and the “Draw Filled Zones” tool.

Click in the editor to place the first corner and then the Copper Zone Properties dialog will appear. Select the GND net and both F.Cu and B.Cu and click Ok.

Then draw a rectangle around the Edge.Cuts rectangle. It should look like this.

Currently, it hasn’t actually filled in any of the ground plains, but has only defined the edges. Press the “b” key to generate all filled areas. Make sure the “Show Filled Zones” button is selected and then you should see the Ground Plane.

Vias #

This design is so simple, we didn’t need any Vias to wire anything. However, for the sake of the example, we will place a via to connect the two ground planes even though they are already connected at the through hole components. Generally, you only want to add one via to connect ground planes to avoid creating ground loops. There are some exceptions however. shielding for transmission lines is a good example. So take it with a grain of salt. There are two ways to place Vias

Free-Standing Vias: Use the Free-Standing Via tool to place a via at any location. It will connect whatever nets it is placed in whether or not that is correct.

Here, we can use it to place a via in the middle of the board under the TL081.

Vias Durring Routing: The most common way to place vias is while routing. Press the “x” key to start a route. Then while drawing press the “v” key to prepare a via and click to place the via. The tool will automatically swap layers.

Silkscreen #

It’s always a good idea to add some information to the PCB to help identification. Using the F.Silkscreen and B.Silkscreen layers we can add some text such as a revision number and date.

Design Rule Check (DRC) #

At this point our design is “complete”, but it may have some mistakes in it. We can check our design against the design rules (the settings we set from the Fab capabilities) by running the design rule checker. Click the “Design Rule Checker” button.

Then run the DRC.

In our example, we have no errors, and 6 warnings. All of the warnings are caused by the silkscreens for the J1 and pot are getting cutoff. Not a problem since we did that by intention. Now, we can sign-off and say our design is done.

Exporting Files for the Fab #

Most Fabs require Gerber files to build the PCB. Some fabs will require slightly different configurations, but in general they all follow about the same steps. In the top menu bar select File -> Fabrication Output -> Gerber. This will open the Plot dialog.

Plot the Gerber files and also open the Generate Drill Files dialog and Generate the drill files.

We can check the files look right by opening the Gerber files in the KiCad Gerber File Viewer. Here they look good so we can send them off to the fab.

Summary #

Over the past two short tutorials we have gone from design to PCB. It isn’t very hard and just takes a little practice. Of course, there are many subjects in here that we did not cover. In particular, simulations, multi-sheet schematic hierarchy, custom symbols and footprints, and RF PCB design are some particularly useful topics. However, what we did cover is enough to make simple PCBs. Good luck on your next PCB adventures.

Condensed KiCad PCB Editor Hotkeys #

All hotkeys (key maps, shortcuts) can be found in listed (and editable) Preferences under Hotkeys. However, for convenience, below is a table of a few of the most useful default hotkeys.